EK-V6-ML631-G-J【PDF 8/65 页】VIRTEX-6 HXT FPGA ML631 EVAL KIT

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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics

SelectIO? DC Input and Output Levels

Values for V IL and V IH are recommended input voltages. Values for I OL and I OH are guaranteed over the recommended

operating conditions at the V OL and V OH test points. Only selected standards are tested. These are chosen to ensure that

all standards meet their specifications. The selected standards are tested at a minimum V CCO with the respective V OL and

V OH voltage levels shown. Other standards are sample tested.

Table 7: SelectIO DC Input and Output Levels

I/O Standard

V, Min

V IL

V, Max

V, Min

V IH

V, Max

V OL

V, Max

V OH

V, Min

I OL

mA

I OH

mA

LVCMOS25,

LVDCI25

LVCMOS18,

LVDCI18

LVCMOS15,

LVDCI15

LVCMOS12

HSTL I_12

HSTL I (2)

HSTL II (2)

HSTL III (2)

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

0.7

35% V CCO

35% V CCO

35% V CCO

V REF – 0.1

V REF – 0.1

V REF – 0.1

V REF – 0.1

1.7

65% V CCO

65% V CCO

65% V CCO

V REF + 0.1

V REF + 0.1

V REF + 0.1

V REF + 0.1

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

0.4

0.45

25% V CCO

25% V CCO

25% V CCO

0.4

0.4

0.4

V CCO – 0.4

V CCO – 0.45

75% V CCO

75% V CCO

75% V CCO

V CCO – 0.4

V CCO – 0.4

V CCO – 0.4

Note(3)

Note(4)

Note(4)

Note(5)

6.3

8

16

24

Note(3)

Note(4)

Note(4)

Note(5)

–6.3

–8

–16

–8

DIFF HSTL I (2)

DIFF HSTL II (2)

–0.3

–0.3

50% V CCO – 0.1 50% V CCO + 0.1

50% V CCO – 0.1 50% V CCO + 0.1

V CCO + 0.3

V CCO + 0.3

–

–

–

–

–

–

–

–

SSTL2 I

SSTL2 II

DIFF SSTL2 I

DIFF SSTL2 II

SSTL18 I

SSTL18 II

DIFF SSTL18 I

DIFF SSTL18 II

SSTL15

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

V REF – 0.15

V REF – 0.15

50%

V CCO – 0.15

50%

V CCO – 0.15

V REF – 0.125

V REF – 0.125

50%

V CCO – 0.125

50%

V CCO – 0.125

V REF – 0.1

V REF + 0.15

V REF + 0.15

50%

V CCO + 0.15

50%

V CCO + 0.15

V REF + 0.125

V REF + 0.125

50%

V CCO + 0.125

50%

V CCO + 0.125

V REF + 0.1

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V CCO + 0.3

V TT – 0.61

V TT – 0.81

–

–

V TT – 0.47

V TT – 0.60

–

–

V TT – 0.175

V TT + 0.61

V TT + 0.81

–

–

V TT + 0.47

V TT + 0.60

–

–

V TT + 0.175

8.1

16.2

–

–

6.7

13.4

–

–

14.3

–8.1

–16.2

–

–

–6.7

–13.4

–

–

–14.3

DIFF SSTL15

–0.3

50% V CCO – 0.1 50% V CCO + 0.1

V CCO + 0.3

–

–

–

–

Notes:

1.

2.

3.

4.

5.

6.

Tested according to relevant specifications.

Applies to both 1.5V and 1.8V HSTL.

Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.

Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.

Supported drive strengths of 2, 4, 6, or 8 mA.

For detailed interface specific DC voltage levels, see UG361 : Virtex-6 FPGA SelectIO Resources User Guide .

DS152 (v3.6) March 18, 2014

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